STEPFPGA
A miniature FPGA development core board for beginner
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A miniature FPGA development core board for beginner
Last updated
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STEPFPGA MXO2Core is a miniature FPGA development core board designed based on Lattice MXO2-4000 FPGA chip. The embedded components such as LEDs, segment displays, switches and pushbuttons help users tangibly interact and observe experimental results. The DIP40 footprint features the flexibility to expand projects on breadboard or embed the board for your products. STEPFPA MXO2Core is also extremely user friendly for FPGA beginners where you can develop lots of FPGA projects using our cloud-based Web IDE (Verilog) with simple interface and abundant pre-built examples.
MXO2Core is small yet powerful. The following diagram illustrated the components layout on the board and pin diagram definitions:
For beginners, the MXO2Core board are good for implementation of fundamental digital circuits appeared in your curriculum textbooks such as Logic Gates, Decoders, Multiplexers, Flipflops, Counters…With the 36 GPIO pins and maximum of 400MHz clock frequency (boosted by the internal PLL), you can add many extension modules to explore advanced applications such as industrial controls, communications, signal processing and synthesis.
Board Name
STEPFPGA-MXO2Core
FPGA Chip
LCMXO2-4000HC
FPGA Manufacturer
Lattice Semiconductor
Resources
4320 LUTs
Block RAM
92Kbit
User Flash
64Kbit
GPIO (3.3V)
36
Hard IP-cores
SPI, I2C, Timer
Supporting Soft cores
MICO8/32, 8051
IDE Tools
WebIDE, Diamond IDE
Burning Program
USB MSD (Flash drive)
There are two IDE tools available to develop the board.
This is the program for default after-factory setting. Plug in STEPFPGA to your computer and drag this file into the MSD drive.
is a recommended tool for FPGA beginners, which is a cloud-based simplified tool integrated with all essential features to implement digital circuits.
The software offers leading-edge design and implementation tools optimized for low-power FPGA architectures. The free license enables users to design and evaluate the performance of non-SERDES based Diamond supported devices.
