> For the complete documentation index, see [llms.txt](https://support.eimtechnology.com/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://support.eimtechnology.com/quick-access/webide.md).

# WebIDE

A cloud-based simplified tool to implement digital circuits.

Go to [WebIDE](https://stepfpga.eimtechnology.com/) page

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FY6xpJ13fv58Fhp1n8OZv%2Fimage.png?alt=media&amp;token=9b28bafb-052b-40f6-845b-31770a351dcd" alt=""><figcaption></figcaption></figure>

## Demo Videos

{% embed url="<https://www.youtube.com/watch?v=Hs74K9Sf7wA>" %}

{% embed url="<https://www.youtube.com/watch?v=1dwpKoTp4Zo>" %}

## Instruction

### Step1

Start your FPGA project on WebIDE and click “Start” to create a new project&#x20;

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FCYRMHUvdntnI5IC1YiQ2%2FScreenshot%202023-09-21%20155638.png?alt=media&amp;token=2f1e62e3-f540-43ae-b401-7573b1282b01" alt="" width="563"><figcaption><p>Step1</p></figcaption></figure>

### Step2

Create a project

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FV7NqmQJY1Nd8vy0g0UJA%2FScreenshot%202023-09-21%20155803.png?alt=media&amp;token=2ded572b-a97f-4971-9c72-17cb859dafe2" alt="" width="563"><figcaption><p>Step2</p></figcaption></figure>

### Step3

Create a Verilog design file

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FwxmESv4EEUbdMnl1wO7Y%2FScreenshot%202023-09-21%20155907.png?alt=media&amp;token=68ef87f0-1e3b-48bc-934d-d4da2cdf13df" alt="" width="563"><figcaption><p>Step3</p></figcaption></figure>

### Step4

Code editing

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FSHluUtdymroxc7ijNW56%2FScreenshot%202023-09-21%20155951.png?alt=media&amp;token=d40461ab-546f-494c-824d-ba45ceffb6b4" alt="" width="563"><figcaption><p>Step4</p></figcaption></figure>

### Step5

Logic Synthesis

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FOTWfPNZ8HitOM3YeoG8b%2FScreenshot%202023-09-21%20160040.png?alt=media&amp;token=56a32bc5-845d-42b8-b7cb-7379c97021fe" alt="" width="563"><figcaption><p>Step5</p></figcaption></figure>

### Step6

Pin assignment.

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2Fz7g8VEDLEaDRpuW4gODk%2FScreenshot%202023-09-21%20164226.png?alt=media&amp;token=8591dcb0-4081-45c1-94f4-65fb53e32e73" alt="" width="563"><figcaption><p>Step6 part1</p></figcaption></figure>

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2F1D639EO7dCYWjl5iV2y5%2FScreenshot%202023-09-21%20163129.png?alt=media&amp;token=81bdb223-1dc5-41ef-bf5e-fb7006123d13" alt="" width="563"><figcaption><p>Step6 part2</p></figcaption></figure>

### Step7

Check for FPGA internal routing summary information

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FH2bm6HTZrbQMcJrTmZMQ%2FScreenshot%202023-09-21%20164357.png?alt=media&amp;token=756a1476-2385-48e5-a0e4-ec0b3cd3e623" alt="" width="563"><figcaption><p>Step7</p></figcaption></figure>

### Step8

Burn the code into STEP FPGA board

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FHyOTpjqSbJiXp5NVWUg9%2FScreenshot%202023-09-21%20164457.png?alt=media&amp;token=ce00e953-b0a5-4fd6-a625-85b5ca950493" alt="" width="563"><figcaption><p>Step8</p></figcaption></figure>

## Some Tips

{% tabs %}
{% tab title="Quick Design" %}

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2Fq5SF0KuYIf1kzZXhcjT9%2FScreenshot%202023-09-21%20160214.png?alt=media&amp;token=e6389c97-dd1d-400d-a36e-b9eafabe3ea6" alt=""><figcaption><p>Quick design</p></figcaption></figure>
{% endtab %}

{% tab title="Manage Work Pieces" %}

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FB6XlG7GzEFx4AzUWcjYw%2FScreenshot%202023-09-21%20160320.png?alt=media&amp;token=a80b69b2-8338-45a7-acda-03101d66b552" alt=""><figcaption><p>Manage work-pieces</p></figcaption></figure>
{% endtab %}

{% tab title="Debug Information" %}

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FW7b7mkR4nBsEPrIVy80y%2FScreenshot%202023-09-21%20160426.png?alt=media&amp;token=b616ae77-cb5f-4ecb-876b-331bc7e2298b" alt=""><figcaption><p>Show the debug information</p></figcaption></figure>
{% endtab %}

{% tab title="Trace Error" %}

<figure><img src="https://2395483440-files.gitbook.io/~/files/v0/b/gitbook-x-prod.appspot.com/o/spaces%2FFcgTb7Dst30iGr6yQqof%2Fuploads%2FUE9YeMZ5MEz8p9krkwXH%2FScreenshot%202023-09-21%20160544.png?alt=media&amp;token=96e2659b-d66e-483f-99ab-adf5cd2a5019" alt=""><figcaption><p>Trace error</p></figcaption></figure>
{% endtab %}
{% endtabs %}